1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device, and more specifically to a manufacturing method of a semiconductor device by processing of a wafer level.
2. Description of the Related Art
A method for manufacturing a semiconductor device by processing of a wafer level has been performed as a method for manufacturing a semiconductor device of a chip size package etc. For example, as a method for manufacturing a chip size package using processing of a wafer level, there is a following manufacturing method of a semiconductor device of a chip size. That is, in a semiconductor wafer, a rewiring pattern is formed so that it is electrically connected to electrode terminals of individual semiconductor chips formed in the semiconductor wafer, and an external connection terminal is formed so that it is electrically connected to the rewiring pattern. Then a surface in which the external connection terminal of the semiconductor wafer is formed is sealed by resin, and the semiconductor wafer is cut into individual segments together with the resin after the sealing (for example, see JP-A-10-79362 and JP-A-8-330313).
In the method for manufacturing a semiconductor device by such a processing of a wafer level, a plurality of semiconductor devices with the same structure are formed on the semiconductor wafer in arrangement aligned in length and width. These semiconductor devices are mounted on a substrate etc. respectively, after being cut into individual segments. Before the semiconductor devices are mounted on the substrate etc., conformity and nonconformity of electrical characteristics etc. of the respective semiconductor devices are judged by inspection and only conforming semiconductor devices are mounted on the substrate etc. Incidentally, inspection for judgment of conformity and nonconformity of a product is actually made at each stage of a manufacturing process of the semiconductor device. For example, at a stage of manufacturing the semiconductor wafer, inspection of conformity and nonconformity of electrical characteristics etc. of individual semiconductor chips formed in the semiconductor wafer is also made (for example, see JP-A-2004-31463).
As described above, product inspection is made at each of the manufacturing stages in the manufacturing process of the semiconductor device. For example, at a stage of manufacturing the semiconductor wafer, characteristics of individual semiconductor chips are also tested. However, in the related-art manufacturing process of the semiconductor device of a wafer level, regardless of an inspection result at a stage of the semiconductor wafer, rewiring patterns or external connection terminals are formed with respect to all the semiconductor chips. That is, the rewiring patterns or external connection terminals are formed with respect to semiconductor chips judged as conforming product and also with respect to semiconductor chips judged as nonconforming product. This is because in the manufacturing process, it is difficult not to form the rewiring pattern etc. on only the semiconductor chips judged as nonconforming product. Generally, a resist pattern for forming the rewiring pattern is formed by a photolithographic process using an exposure mask. Therefore, in order to perform exposure so as not to form the resist pattern on the nonconforming semiconductor chips, a mask with special shape in which an unexposed portion is provided in accordance with a position of the nonconforming semiconductor chips must be prepared. Since occurrence positions of the nonconforming semiconductor chips vary depending on the respective semiconductor wafers, it is actually impossible to prepare such a mask with special shape.
Then, after the required rewiring patterns or external connection terminals are formed, electrical characteristics or appearances, etc. of individual semiconductor device formed on the semiconductor wafer are inspected.
Thus, in the related art, the rewiring patterns etc. are formed to manufacture the semiconductor device at a wafer level regardless of the inspection result of the semiconductor chips at the manufacturing stage of the semiconductor wafer. Therefore, there were problems that in the case of inspecting a formed semiconductor device, accurate inspection cannot be made or an inspection apparatus is damaged or adverse influence on other conforming semiconductor device is had.
For example, when burn-in of a semiconductor device is performed in the case that a nonconforming semiconductor chip is electrically short-circuited, there arise problems that an overcurrent flows in a semiconductor device equipped with its nonconforming semiconductor chip thereby damaging an inspection apparatus or a conforming semiconductor device disposed near to the nonconforming semiconductor device comes under the adverse influence of the nonconforming semiconductor device thereby becoming a nonconforming semiconductor device.